You write custom CUDA kernels to replace PyTorch operators for speedups.
Implement Channel RMS Gate on NCHW tensors: For input x[N,C,H,W], compute per-(n,c) RMS over spatial dims r = sqrt(mean(x^2 over H*W)), then gate g = sigmoid(gamma[c]*r + beta[c]), and output y = x * g broadcast over H*W. One CUDA block should handle a single (n,c), perform warp-level reduction for the RMS using shuffles, and apply the gate to all spatial elements in the same kernel. Provide a PyTorch reference using nn.Parameters for gamma and beta. Ensure accuracy within rtol=1e-3.
